Memory systems using tunnel diodes



Aug. 17, 1965 J. c. MILLER MEMORY SYSTEMS USING TUNNEL DIODES Filed June le, 1959 2 sheets-sheet 1 Z6 /f/z//VG WIP/ff Z4 :omrf- Jaz/erf- Azff/f/#M J/oa l v E 52 q 55 9' INVENTUR. 5i J JAMES II. MILLER L? BY Z y Aug. 17, 1965 J. c. MILLER MEMORY SYSTEMS USING TUNNEL DIODES Filed June 16, 1959 2 Sheets-Sheet 2 mz mf/y iff/m' foams Y1 Paw .iff/iff .Wirf

1N VEN TOR. .JAMES E. MILLER BYMMMHW rrai/viy United States Patent O 3,2tlil595 MEMRY SYSTEMS lUSlNG TUNNEL BEBES .lames Coheaii Miller', Hamiiton Square, NJ., assigner to Radio Corporation of America, a corporation of Beiaware Filed .lune lo, i959, Ser. No. 32?,o72 io Claims. (Ci. 367-885) This invention relates to memory systems, and particularly to memory systems using semiconductor storage elements.

Prior memory systems include those of the so-called diode-capacitor type. In these prior memories, binary ii formation is represented by the stored charge or absence thereof in the capacitor elements. For example, the two binary digits may be represented by the presence or absence, respectively, of any appreciable stored charge. One of the problems with memory systems of the diodecapacitor type involves the leakage of the stored charge in a inite period of time. One method used to reduce the amount or" leakage is to use high resistance elements, say in the order of a megohm or more, rather than lower resistance elements, connected in the discharge path of each capacitor. However, in relatively large memory systems, a myriad of such resistances are required in order to avoid all possible low resistance discharge paths. Even with these high resistances, the stored information still is required to be regenerated after a given time interval. The regeneration operation includes reading each storage portion of the memory, determining the digit stored in that position, and then rewriting the same digit back into the same storage position. it is desirable to avoid such regeneration operation. Also, the high discharge resistance increases the power loss of such prior systems.

It is an object of the present invention to provide improved memory systems ot the diode-capacitor type.

mother object of the present invention is to provide improved memory systems o a diode-capacitor type capable of retaining stored information without requiring any regeneration operations.

A further object of tue present invention is to provide improved memory systems of the diode-capacitor type capable of operating at a relatively' high speed and which use relatively small power in their operation.

in accordance with the present invention, the information is stored in a ield storage type device such as a linear capacitor or a linear inductor, or both, and the stored information is retained in the device by means of a hold circuit including one or more negative resistance diodes coupled to the storage device. Any suitable means may be used for applying the desired storage signal to the storage element. According to a further feature of the invention, the storage device is arranged in a tuned circuit with the information being represented by the presence or absence, respectively, of oscillations.

In the accompanying drawings:

FIG. l is a schematic diagram of one embodiment of a memory system according to the invention;

FIG. 2 is a schematic diagram of another embodiment of a memory system according to the invention having a Write source differently connected from that of FIG. 1;

PEG. 3 is a schematic diagram ot the current versus voltage characteristic curve for a negative resistance diode suitable for use in the system of FiG. i;

FIG. 4 is a schematic diagram in sectional view of one form of negative resistance diode suitable for use in the present invention;

FIG. 5 is a composite current versus voltage characteristic of the two series-connected negative resistance I diodes of FIG. i;

Patented Aug. l. 7, i965 FIG. 6 is a schematic diagram of another embodiment ot a memory system according to the invention using an inductance element;

FIG. 7 is a schematic diagram of an embodiment of the invention using a pair of negative resistance diodes with their cathodes connected to a common junction in back-to-back relation;

FIG. 8 is a schematic diagram of an embodiment of the invention using a single resistance diode in conjunction with a tuned circuit;

FIG. 9 is a schematic diagram of an embodiment of the invention using a single negative resistance diode in conjunction with a storage capacitor; and

FlG. 10 is a schematic diagram of a memory array using a negative resistance diode.

The memory system of FIG. l includes an information storage device, such as a linear capacitor I2, having its upper plate connected at a junction point 14. The lower plate of the capacitor 12 is connected to a point of common reference potential, indicated in the drawing by the conventional ground symbol. A decoupling element 15 connects the junction point 14 to a hold circuit I6. As indicated in the drawing, the decoupling element l5 may be a conventional diode rectier, connected for easy direction of positive conventional current flow from the hold circuit to to the junction point ld. The diode serves to retard the discharge of the capacitor 12 in the high voltage state, as described more fully hereinfater. If desired, the decoupling element may be a linear resistor. ln practice, a decoupling element having an impedance ot from l() to i080 ohms at the `operating frequency is suitable. The hold circuit serves to maintain the storage device in a desired set condition. In FIG. l, the hold circuit lo includes a pair of negative resistance type diodes i3 and 2? connected in series with each other in the same sense. The decoupling element l5 is connected to a midpoint 22 between the two diodes i3 and 20. An energizing source 24 is connected across the hold circuit 16.

Binary information is stored in the capacitor 12 by means of a write source 26 which is resistor-coupled via a decoupling resistor 27 to the junction point i4. A pair of output terminals 25 are connected across the storage capacitor I2. The write source 26 and the energizing source 245 each is provided with a ground connection.

rihe energizing source 24 may be any source of periodic energizing signals, for example, a sinusoidal source, or a unidirectional pulse type source having a suitable repetition rate. Preferably, the energizing source Z4 is of the constant-voltage type, and the write source 26 is of the constant-current type. However, a constant-current source may be used for both the sources 2d and 26, if desired. A suitable constant-current source for the energizing source 2d is one having an internal impedance of the same order as the average positive resistance value of the diodes as described more fully hereinafter. For eX- ample, germanium type diodes may have an average positive resistance of from l to l() ohms.

The lwrite source 26 also may be resistor-coupled to the mid-point 22 of the hold circuit lo as shown in the embodiment 'of FIG. 2. The other elements of FIG. -2 are arranged similarly to those of FIG. l. In FIGS. l and .2 and each ot the other iigures herein corresponding elements are designated by Icorresponding reference numerels.

The characteristic curve 28 of FIG. 3 represents a plot of the current lowing through a negative resistance diode as a function of the .applied voltage .across the diode. The `curve 28 has a negative resistance region between the points b and c and two positive resistance regions between the points a, b and c, d, respectively. The reciprocal oi the average slope of the positive resistance regions n,

b .and c, d corresponds to the average positive resistance value of the diodes 13 and 20 as indicated by the lines 29 and 30. In the region Vl to V2 of t-he characteristic curve 28 of FIG. 3 energizing voltages increasing in amplitude .above the critical value Vl cause a corresponding decrease in diode current flow from arelatively high value I1 towards a relatively low value I2 due to fthe negative resistance ofthe diode. Further incre-ases of the energizing voltage above Vthe value V2 cause further increases ofthe diode current in conventional fashion. The point b at a maximum of the characteristic curve represents a so-called break point. The negative resistance diodes may be of the type described by L. Esaki in an article published in the Physical Review, Volume 109, page 603 (.1958). The characteristic curve 23 is exhibited by a semiconductor diode of the degenerate type having a narrow or abrupt junction. f

Another type of negative resistance diode is shown in crosssectional view in FIG. 4. The diode of FIG. 4 may be fabricated as follows: a single crystal bar of n-type germanium is doped with arsenic to have a donor concentr-ation 4.0 1019 .cin-3 by methods conventional in the semiconductor art. This may be accomplished, for example, by pulling a crystal from molten germanium containing the requisite concentrationof arsenic. A wafer 31 is cut from the bar along the 111 plane, i.e. a plane perpendicular to the 111 crystallographic axis of the crystal. The wafer 31 is etched to a thickness of about two mils in -a conventional etch solution. A major surface of the wafer 31 is soldered to a strip 35 of nickel, with `a Iconventional lead-tin-arsenic solder, to provide a non-rectifying contact between the wafer 31 and the -strip 35. i The nickel strip 35 serves eventually as a base lead. A five mil diameter dot 31 of 99 percent by weight indium, 0.5 percent by weight zinc and 0.5 percent by weight gallium is placed with a small amountof a commercial flux on the free surface 33 of the germanium--wafer 31 and then heated at 450 C. for one minute in an atmosphere o-f dry hydrogen to alloy a portion of the dot to the :free surface 33 of the wafer 31, and then cooled rapidly. In the alloying step, the unit is. heated and cooled as rapidly as possible so as to produce an abrupt p-n junction 38. The unit is then given a iinal dip etch for five seconds in a slowiodide etch solution, followed Vby rinsing in distilled water. A suita-ble slow iodide etch is prepared by mixing one d-rop of a solution comprising 0.55 gram potassium iodide, and 100 cm.3 water in l0 cm.3 of a solution comprising 600 cm.3 concentrated nitric acid, 300 cm.3 concentrated aceticacid, and 100 cm.3 concentrated hyd-roiluoric acid. A pigtail connection may be soldered tothe dot where the device is to be used at ordinary frequencies. Where the device is to be used at high frequencies, contact may be made to the dot 37 with a low impedance lead.

The curve 39 of FIG. 5 is a composite characteristic curve, as seen from the energizing source 24, of the two series-connected diodes 18 and 20 of FIG. 1. The curve 39 represents the condition wherein one of the diodes 1S and 20 breaks before the other. If the two diodes 18 and 20 exhibited identical characteristics, both would break Vat approximately the same energizing voltage and the composite characteristic between the points e and f would be that somewhat as represented by the dotted line 40. In practice, however, the circuit is arranged -so that only one of the diodes 18'and 20 breaks at a time. Thus, the entire solid curve 39 is the one of interest inthe present invention. The load line 41 of the curve A relatively high voltage V3 appears at the junction point 14 when the lower diode 20 breaks first, and a relatively low voltage V4 appears at the junction point 14 when the upper diode 18 breaks rst. The decoupling element 15 effectively limits any discharge current ilow in a path including the storage capacitor 12, the decoupling element 15, the hold circuit mid-'point 22, the diodes 18 and 20, and the common ground.

The write source 26 is used to select the one of the two diodes 18 and 20 vwhich breaks rst. A current of one polarity, for example, positive owing in the conventional direction from .the write source to the junction point 14, causes the lower diode 20 to break first. The relatively high voltage V3 (FIG. 5) is then applied across the storage capacitor 12. The write signal either is made of longer duration Vthan an energizing pulse, or is synchronized by any suitable means (not shown) to occur during the negative phase of an alternating polarity energizing signal. VPreferably, the write source 26 in FIGURE l is synchronized with the energizing source. The Write pulse leadingedge is transmitted via the distributed capacitance (not indicated) of the decoupling element diode yto the junction point 22. The lower diode 20 is held at the thus 39 corresponds to the normal operating condition when Y set operating point by the signals of positive polarity from the energizing source 24. A negative polarity write current pulse applied fromthe write source 26 to the junction point 14 causes the upper diode 1S to assume the high voltage condition. The storage capacitor 12 (FIGURE l) then discharges through the writesource 26 to the relatively small `amplitude voltage V4V (FIG. 5) developed across the lower diode 20. 'Again, the energizing signals hold the diode 18 in the high voltage condition even after termination of the -write signal. The positive and negative write pulses may be of relatively large amplitude to perform the Writing operation in a relatively short time, say as fast as one to ten millimicroseconds. Note that by discharging the capacitor 12 through the write source 26, that the writing spe-ed is independent of the frequency or repetition rate of the energizing source 24.

Accordingly, the storage capacitor 12 is charged either to the relatively high voltage V3 or the relatively low voltage V4 in a one-to-one.correspondence with the positive and negative polarity write signals from the source 26. The hold circuit 16 operates to maintain the capacitor 12 at the set value until a new write cycle is applied to the memory circuit. The maximum frequency, in case s age condition-due to the Vinternal Vcapacitances of'theV material itself. These internal capacitances, for a given negative resistance type diode; may vary between, say and 1,000 micro-microfarads. Accordingly, the en- Vergizingrsonrce '24 is chosen so that the RC time constant of the negative resistance diodes is relatively short compared to `a half-cycle of a sinusoidal zsource, or to the spacing interval between successive pulses for a pulse source. Each write signal applied by the write source 25 is made of an amplitude large enough so that Vthe diode 20 is brought to either the high or the low voltage condition regardless of its previous state. That is, each new write `signal overrides any previously stored write signal to cause the storage capacitor 12 to assume either the high or Vthe low voltage state in correspondence with the new write signal.

The memory system 50 of FIG. 6 is similar to that of the system of FlG. -2 except that the storage device isV provided byja tuned circuit 51. VThe tuned circuit 51 includes a variable inductance element 52and a capacitor 53. The tuned circuit capacitor 53 may be provided by the distributed capacitance of the inductance element52, indicated by the dotted capacitor 53. VThe inductance of element 52 is tuned to resonate at the frequency of theV energizing source signals. A series tuned or a parallel tuned circuit may be used. For example, the capacitor 53 may be an external capacitor connected in series with or in parallel with the inductance element 52 to provide the tuned circuit 51.

The mode of operation of the circuit of FIG. 6, however, is dilerent from that of the circuits of FIGS. 1 and 2. When a negative polarity write signal is applied, the lower diode is changed to the -relatively low voltage condition and no voltage, or at most, a relatively small voltage, is applied across the storage inductor 52. This relatively small amplitude signal appearing across the output terminals 28 represents one of the stored digits. When a positive polarity write signal is applied, the lower diode 2G is changed to its high voltage condition and a relatively high voltage is applied across the inductor 52. This relatively high voltage is 4applied to the tuned circuit S1 and excites the tuned circuit 51 to resonance. The frequency of the energizing source 24 is at or close to the resonant frequency of the tuned circuit S1, and therefore, each positive polarity signal from the energizing source 24 together with the energy stored in the tuned circuit 51 sustains the resonance. The oscillations of the tuned circuit 51 build-up to a relatively large amplitude. The tuned circuit 51 remains oscillating until a new negative polarity write signal is applied to quench the oscillations. The storage of the other binary digit thus is represented in the memory circuit 50 by continuous oscillations appearing across the output terminals 28.

The negative resistance diodes of the hold circuit can also be connected in back-to-baclc relation as shown for the hold circuit 54 of FIG. 7. In the hold circuit S4, the diodes 18 and 20 each have like electrodes, for example, their cathodes connected at the mid-point 22. The remaining portions of the memory system of FIG. 7 may be similar to those of the previously described .emory circuits.

The operation of the memory system of FIG. 7 is similar to that described for the memory system of FIGS. 1 and 2. Either a relatively large or a relatively small output voltage appears across the output terminals 28 to represent the storage of the one and the other binary digits, respectively.

The hold circuit also may be arranged to have a single negative resistance diode as shown for the hold circuits 56 and 58 of FIGS. S and 9, respectively. In each of these hold circuits, a single negative resistance diode 59 has one electrode, for example, the anode connected to the output of the energizing source and has the cathode connected to ground. The anode of the negative resistance diodeV 59 is coupled via the decoupling element 15 to the junction 14. The memory system of FIG. 8 includes the tuned circuit storage device S1, and the memory system of FIG. 9 includes the capacitor storage device 12.

The operation of the circuit of FIG. S is similar to that described for the system of FIG. 6 except that it does not provide gain. That is, in the system of FIG. 6 using a pair of negative resistance diodes 18 and 20, the output signal appearing across the output terminals 28 may be of larger amplitude, currentwise, than that of the write signal used to establish the storage device in a desired one of the two stable states. In the system of FIG. 8 however, using a single negative resistance diode, the output signal appearing across the output terminals 2S is of about equal amplitude, current-wise, to that of the write signals used to set the device into the desired stable states.

The memory system of FIG. 9 operates in the manner described above for the systems of FIGS. 1, 2 and 7 With the exception that the system of FIG. 9 does not provide current gain.

A plurality of the memory systems of the invention may be advantageously arranged in a two-dimensional storage array as indicated in the exemplary array 6d of FIG. l0.

The .array 60 has, for example, a 4 x 4 array of memory systems 1d', each similar to that of FIG. 2 with the exception that the decoupling element I5 is provided by a linear resistor. The sixteen memory systems lil are used to store eight binary digits. The four systems itl' in the odd numbered rows of the array 6l) are paired with the four systems 1d' in the even numbered rows of the array 60. A common energizing source 24 is coupled to all the memory systems liti' of the array. A common ground return is provided between each of the Systems Iii' and the energizing source 24. The systems lil of the irst and third rows have their junction points 14 coupled via a different one of eight decoupling resistors 64 to a first input on a diiierence amplifier 66. The junction points id' of the second and fourth rows are similarly coupled via a diiferent one of eight decoupling resistors 67 to the second input of the difference amplifier 66. Because the same binary digit is stored in an odd row and a paired even row system 19', the sum of the inputs on the first input of the difference amplifier d6 equals the sum of the inputs on its second input. A column select source 68 and a row select source 71 are used to write a binary digit into a desired one of the memory elements 10 in coincident current fashion. The four outputs of the column select source 63 are connected respectively to the four column lines 69 of the array 6). A diierent decoupling resistor 7d couples the respective column lines to the respective mem ory systems 10'. The row select source 71 is provided with tirst and second pairs of output lines. The rst pair of output lines x1 and x2 are coupled via different decoupling resistors 72 to the junction points 14 of the first and third rows, respectively, of memory systems lll. The second pair of row output lines y1 and y2 are coupled via separate decoupling resistors 74 to the junction points 14 of the second and fourth rows, respectively, of memory systems 16.

Information is written -into both systems l0 of a desired pair of memory systems 1d by concurrently applying a signal to the one column line 69 linking 'these desired systems i0' and concurrently applying a like polarity signal to the one x and one y line of that pair of systems 10. The coincidence of the column and row signals at the desired pair of memory systems l0' causes the one or the other of the diodes 1S and Ztl to break down in each of these systems 10', thereby storing the desired binary digit.

The stored information is read out from any desired pair of memory systems lll by activating the one column line 69 and one but not both of the x or y lines of that pair of systems 10. For example, the one row line activated during a read operation may be the row line x2 for the pairs of systems Id of the rst and third rows, or the row line y2 for the pairs of systems lil of the second and fourth rows. The one column line and the one row line currents are together of sutlicient .amplitude to change one of the systems tu' of the selected pair to one state, say, the high voltage state. If the selected systems 1li were initially in the high voltage state, there is no net change of voltage across the differential amplifier 56. If the selected systems lil were initially in the low voltage state, a relatively large amplitude signal change appears across the differential amplifier 66. In the latter case, after the read operation is terminated, the selected row and column lines may be activated with opposite polarity currents to return the changed system lil' to its initial low voltage condition.

New information may be written into the same or any other pair of systems 10' by applying suitable polarity writing signals to the column and row lines of that pair of elements.

What is claimed is:

ll. A memory system comprising a field effect storage device having two operating states, a hold circuit including a negative resistance diode element, said diode having a high and a low voltage operating state correspond-ing to the one and the other offsaid storage device operating states, a decoupling element connecting said diode to'said storage device, means coupled tosaid stor-` age device and also coupled across said diode to set said storage device to one of its two operating states and to also set said diode in the corresponding one of saidY high and low states, and means for applying energizing signals across said diode to maintain said set state.

v2. A memory system includingla tield effect storage device having two operating states,` a hold lcircuit including a pair of negative resistance diodes each having high and low voltage states, a junctionpoint, said diodes being connected to each other at said junction point, a decoupling element connecting said junction point to said storage element', and means coupled to said storage device and to said junction point for setting said storage device in one of said two states and for setting said diodes to mutually opposite states corresponding t-o the set state of said storage device.

3. A memory system as recited in claim 2, said storage device being a capacitor.

` energizing Vsignals toall said hold circuits, a plurality` 8 Y signals being voltages of relatively high and low arnplitudes, respectively.

10. A memory system as recited in claim 8, said storage element comprising a tuned circuit, said one and other type signals being the presence and absence of oscillations, respectively. Y l

1 11. A memory system as recited in 'claim 8, said hold circuit including a pair Yof negative resistance diodes connected in series with each other, and said rst terminal' being connected at a mid-point diodes.

12. A memory system comprising a plurality of memorylelements arranged in a matrix having rows and col-v umns, each of said elements comprising a storage device, a hold circuit including at least one negative resistance diode, and a decoupling element connected between said hold circuitand said storage device, means for applying between said pair Vof of-column lines each coupled to allV the hold circuits of 4. A memory system as recited in claim 2, said storage i device being an inductance element having a distributed capacitance. A l

5.' A memory system as recited-in claim 2, said storage device comprising a tuned circuit.

6. A memory system comprising an inductance and a capacitance coupled to each other in a tuned circuit, a hold circuit comprising a pair of negative resistance diodes each connected at a junction point, said tuned circuit being coupled yacross one of said diodes, means for applying periodic signals across both said diodes, said in-v ductance and capacitance being'tuned frequency of said periodic signals. v l

7. -A memory 4system comprising a storage capacitor, the amount of charge stored in said capacitor representto resonate at the Ving digital information, and means for'n'iaintaining saidV stored charge comprising. ahold circuit having a pair l,of negatlve resistance diodes connected in series with each other at a junction point,- said diodes each having ahighl anda low lvoltage operating state, a decoupling element connecting said junction point to said capacitor, means for applying energizing signals across saiddiodes, vand means for setting a desired one of said diodes to said high voltage state and the other of said diodes to said low voltage state, said energizing signals jointly with said stored charge vmaintaining said diodes in said setstates.

3.V A memory system comprising a storage element for Y storing binary information signals, output terminals connected'across' said storage element, a signal of one type being produced across said output terminals when a binary l vsignalV is stored in said element, a signal of another type'being producedacross-said output terminals whenV a binary 0 is stored'in said element, a hold circuit in-` cluding a ,negative resistance diode, said diode havmg high .and low operating states corresponding, respectively, =to storage of said 1 and 0 signals in said storage ele* ment, a decoupling element having affirs't terminal connected Vto said hold circuit and a second terminal connected to said storage element, means for applying write signals across saidv storage element and across said negartive resistance diode to store eitherabinary "1 signal or a binaryv 0 signalinsaid storage element and to set said diode correspondingly in either'its said high or low operating state, and means for applying periodic energiz-V ing signals across said hold circuit to maintain the storage of the thus Written binaryvsignal in said storage element. f

VV9. A memory system as recited in claim 8, said storage element comprising a capacitor, said one and Qhr type a different one of said columns, a plurality of row lines each coupled to all the hold circuits of a diierent one of said rows, and a ditference amplier having tirst and second inputs, said first input being coupled to all the hold storage devices of alternate ones of said rows, and saidV second input being coupled to all the storage devices of the remaining ones of said rows. i

13. A memory system as recited in claim 12, each of said hold circuits including a pa-ir of negative resistance diodes connected in series with each other.

14. A memory system comprising a storage element, a pair of negative resistance diodes, a diode rectier, first and .second junction points, each of said negativeY resistance diodes and said diode rectifier having one electrode 1 connected at said rst junction point, said diode rectier Y other electrode and said storage element being connected at said second junction point, means for applying a pulse of either Vone ory the other polarity to one of said first and second junction points, and means for `applying enenergizing "signals across said pair of negative resistance diodes.

' 15. A memory Vsystem as recitedin claim 14, said pair f of negative resistance diodes being connected in series with each other with corresponding ones of their electrodes being connected to said first junction point.

16.'A memory system as recited in claim 14, said pair of negative resistance diodes being connected inseries with each other with non-corresponding ones of their electrodesbeing connected to said iirst junction point.

References Cited by the Examiner' UNITED STATES PATENTS JouN W. HUCKERT, Primary Examiner.

EVERETT R. REYNOLDS, HERMAN KARL SAAL- -BACH, ARTHUR GAUSS, Examiners. 

1. A MEMORY SYSTEM COMPRISING A FIELD EFFECT STORAGE DEVICE HAVING TWO OPERATING STATES, A HOLD CIRCUIT INCLUDING A NEGATIVE RESISTANCE DIODE ELEMENT, SAID DIODE HAVING A HIGH AND A LOW VOLTAGE OPERATING STATE CORRESPONDING TO THE ONE AND THE OTHER OF SAID STORAGE DEVICE OPERATING STATES, A DECOUPLING ELEMENT CONNECTING SAID DIODE TO SAID STORAGE DEVICE, MEANS COUPLED TO SAID STORAGE DEVICE AND ALSO COUPLED ACROSS SAID DIODE TO SET SAID STORAGE DEVICE TO ONE OF ITS TWO OPERATING STATES AND TO ALSO SET SAID DIODE IN THE CORRESPONDING ONE OF SAID HIGH AND LOW STATES, AND MEANS FOR APPLYING ENERGIZING SIGNALS ACROSS SAID DIODE TO MAINTAIN SAID SET STATE. 